From the book by J. E. Carroll "Solid State Devices" (1980), pages 114 to 117 there is known a process of manufacturing a planar monolithic integrated solid-state circuit comprising at least one insulated-gate field-effect transistor and at least one bipolar transistor whose regions are each implanted in a substrate region of the first conductivity type on the one surface side of a semiconducting substrate of silicon of the second conductivity type. In this process, by means of masked implantations of ions of the corresponding conductivity type, the dopings of the base region and of the emitter region of the bipolar transistor are brought into the first substrate region and those of the source region and of the drain region of the insulated-gate field-effect transistor into the other substrate region, and diffused therein by being activated.
The invention is an improvement on such a process.
The bipolar transistor of the monolithic integrated solid-state circuit manufactured in accordance with the known process, has the disadvantages of an emitter region not centered automatically in relation to the base region, and of a compensated emitter region, so that only relatively small current gain values and low cutoff frequencies are realizable in practice. A non-compensated emitter, according to "Technical Digest IEDM" 1979, pages 514 to 516, in fact offers the advantage that relatively high current-gain values and increased cut off frequencies are realizable in practice. Another disadvantage of the bipolar transistor manufactured in accordance with the known process, is based on a relatively high base resistance as a consequence of an unfavourable distribution of the base region doping which, in turn, has an unfavourable influence upon the cutoff frequency. Finally, the known process according to the aforementioned passage of literature, has the disadvantage that up to the point of manufacturing the electrodes and lead-in conductors of the bipolar transistor, three photoresist making processes are required.